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蒙纳什大学马来西亚校区 / 课程

ECE4063

Integrated circuit design

6 credit pointsLevel 4First semesterMalaysiaDepartment of Electrical and Computer Systems Engineering

基本信息

学分6 credit points
开课学期First semester
校区Malaysia
考核构成
Workshop activities10%
Project15%
Laboratory activities25%
Final assessment40%
Mid-semester test10%

开课安排1

教学期授课方式状态
First semesterTeaching activities are on-campus (ON-CAMPUS)开课

以上为该校区在官方资料中登记的全部开课安排,不是汇总。同一门课可能在多个 教学期开课,也可能不同教学期的授课方式不同。

课程简介

The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. You will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation

以上为 Monash Handbook 的官方原文,版权属 Monash University,此处按本站要求转载并标注出处: 官方页面 ↗

学习成果5

官方原文(Learning outcomes),版权属 Monash University。

  1. ULO1 Describe the fabrication processes used for producing CMOS VLSI circuits.
  2. ULO2 Apply the principles of CMOS Digital Circuits in case studies and problems.
  3. ULO3 Draw a CMOS layout and assess the design in terms of speed, power and area.
  4. ULO4 Predict and optimise the delay in multiple paths of a VLSI design.
  5. ULO5 Design, implement and debug a complex digital design using HDL as part of a team.

教学方式与预期工作量

预期工作量

The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities.

官方原文,版权属 Monash University。

先修 / 同修要求

以下先修关系按官方来源的结构化先修字段解析,原始记号:ECE2131 AND ECE2072

ECE2131Electrical circuits
ECE2072Digital systems

先修链路

按官方先修字段的原始分组展开,AND / OR 的区别保留着—— 「A 或 B」和「A 与 B」在选课时是两回事。每门课点进去可以继续往下看。

以下全部都要
ECE2131Electrical circuits6 cp
以下全部都要
ENG1005Engineering mathematics6 cp
满足其中一项
ENG1002本站暂无这门课的数据
ENG1013Engineering smart systems6 cp
ECE2072Digital systems6 cp

互斥课程1

这些课和本课内容重叠,不能同时算进同一个学位(官方目录的 Prohibition 字段)。选了其中一门,另一门通常只能算选修学分甚至完全不计—— 这跟先修不同,先修是"没修过就不能选",互斥是"修了也不能两门都算"。

ECE5063Integrated circuit design

原始记号:ECE5063

数据来源

数据来源
官方网页
handbook.monash.edu
抓取时间
2026-09-13
可信度
程序抓取,未人工核实

查看官方完整描述 ↗ — 事实性字段(代码、学分、教学期、授课方式、考核权重、先修/同修/互斥关系)与 课程简介、学习成果、教学方式、预期工作量均取自官方 Handbook; 正文版权属 Monash University,此处转载并逐处标注出处。

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